- Design and implementation of high-speed SERDES IPs
- Performing algorithm design, RTL coding, analog design modeling, design verification, synthesis, timing closure, emulation and debugging of chips
- Working with rest of Analog design team for interface definitions.
- Working with the verification team to enable integration into top level test environments and provide support via functional models
- Collaborating with the product development team to get the product into high volume applications.
- Master degree or above in electronic engineering or computer science.
- Work experience and rank are not limited.
- Hands-on experience with 10Gbps and above SerDes is a plus.
- Very strong skills in Verilog RTL coding and simulation.
- Strong skills in scripting (C, Perl, Skill, MATLAB) .
- Self-motivated, good team work spirit and good communication skills.
- Relevant experiences in high speed serdes IO design, Ethernet/PCIe/SATA/USB/MIPI is a plus.
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