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Hardware Verification Manager

Hardware Verification Manager
by Admin on 04-15-2024 at 2:17 pm

Website ArterisIP

Description

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.   

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!   

As a Principal Engineer/Hardware Verification Manager at Arteris your role will be …   

Key Responsibilities: 

  • The role consists of leading the team of verification engineers whose aim is to ensure the verification of a highly configurable IP.
  • He/she defines and improves methods, tool choices and flows to ensure the complete verification of a complex and highly configurable IP.
  • The degree of innovation must enable the regular generation of patents.
  • He/she manages research activities and partnerships with university labs.
  • Team management: recruitment, training, coaching and development of employees.

Experience Requirements / Qualifications:     

  • Design the specifications and architecture of test methodologies for highly configurable circuits.
  • Define, document, develop and execute RTL/coverage verification tests at system level.
  • Manage the development and debugging of advanced test benches
  • Performance verification and power consumption verification
  • Ensure proper execution of regressions and debugging of RTL designs in Verilog and SystemVerilog.
  • Monitor technology and evaluate new verification methods and tools.
  • Supervise collaborations with university labs. Write and draft patents and associated publications.
  • 16+ years experience in digital circuit design and verification.
  • Expert in RTL (Verilog) and UVM/C++ test bench debugging.
  • Experience in integrating supplier-supplied VIPs for unit and system-level verification.
  • Experience with coherent and non-coherent communication protocols and control models (such as AMBA, PCIe, CXL, OCP, others) as well as CPU architectures (ARM/RISC V).
  • Excellent problem-solving, strong communication and teamwork skills,
  • Autonomous, able to work with minimum supervision.
  • Solid knowledge of hardware programming (Verilog/VHDL/System Verilog) and software programming (python/java/scala/c++).

Role Responsibilities 

  • Team management.
  • Specification and architecture of validation flows.
  • Design and development of test benches for complex and strategic IP systems.
  • Optimization of test coverage.
  • System IP debugging.
  • Regress tests, sort tickets and resolve them.

Education Requirements:    

Master’s degree or Doctorate in engineering or computer science.

Other Requirements:   

Candidate should have a valid work permit in the European Union.

Apply for job

To view the job application please visit www.arteris.com.

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