Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
As a Hardware Design Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You’ll create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.
- You are the kind of person that brings your intelligence, motivation, and sense of humor to the office.
- You have been in the ASIC or SoC business for 3 years or more.
- You have a track record of successful deliveries
- You have in-depth knowledge of development in Verilog or VHDL.
- You understand the complete tool-flow from RTL to netlist.
- You are excited about using software to accelerate RTL design.
Experience Requirements / Qualifications:
- BS/MS in Electrical Engineering (MS or above preferred)
- At least 3 years of RTL Design experience related to Arm-based SOC Design
- Understanding of ARM architecture and AMBA Protocols such as APB, AXI, ACE, CHI
- Experience in designing blocks for a high speed SOC
- Experience with industry-standard EDA tools from Cadence, Synopsys, or Mentor
- Experience in designing coherent/non-coherent cache.
- Experience in designing Network On Chip (NOC).
- Experience in timing, area, power optimization.
- Experience with automation using scripting techniques such as PERL, Python or TCL
Estimated Base Salary:
- $130,000 – $144,000 Annually
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.
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To view the job application please visit www.arteris.com.