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Principal Silicon Validation Engineer

Principal Silicon Validation Engineer
by Daniel Nenni on 08-27-2020 at 8:36 pm

Website GlobalFoundries

Summary of Role:

This position is for a Principle Silicon Validation Engineer located at GLOBALFOUNDRIES state of the art campus in Malta, New York. The successful candidate will develop and debug test content used in the process of validating and characterizing new design IP. He or she will develop and debug test content and perform functional characterization during the qualification of advanced technology nodes on GLOBALFOUNDRIES’ strategic roadmap.

Essential Responsibilities:

Test program development, fixture design, test debug, characterization and validation on silicon.
Develop, optimize and sustain test content used in technology qualification, reference design and IP characterization, validation.
Design for Test (DFT) owner, to achieve required test coverage, tester capacity and test time goals. Drive test areas to improve test cell up time, data quality, cost, cycle time, and manufacturing robustness.
Functional test engineering; including tester configuration and calibration control, test program development, pattern generation and ATPG, MBIST, DMA and at-speed transition pattern translation, test methods library development and implementation in C++. Digital CMOS and analog circuit analysis. Test structure design, characterization, debug.
IP validation for yield and performance on single-port, two-port and dual-port SRAMs. Dual-port SRAM characterization for write collision. Compiled memory with MBIST test and DMA test. Reliability test development for High Voltage Stress test, Voltage Droop test and Retention test.
Test program and device failure analysis with digital oscilloscope and functional tester. Test program tuning for electrical fault isolation (EFI), including laser voltage prober, and EFA data correlation. Test program tuning for reliability including HTOL, ESD and Latch-up.
Develop data analysis methodologies to determine root cause of circuit design, yield limitation, parametric performance, defect and functional signals. Provide Silicon Validation reporting across PVT corners, as needed. Test data analysis, including corner lots, voltage and temperature characterization with JMP.
Project management, planning for first silicon bring-up, test hardware vendor and offshore test resource coordinates, test program release and revision control, test operation procedure, hardware setup and program documentation. Peer leadership and mentoring skills.
Candidates will be required to work within a cross functional environment – including process integration, design, advanced process modules, quality, reliability, failure analysis and customer engineering organizations to meet all customer technology requirements, cost and revenue goals.
Perform all activities in safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Qualifications:

Bachelor’s Degree in Circuit Design, Electrical Engineering or related technical field
Four or More Years of Relevant Experience
Fundamental understanding of circuit design, electrical test, and the implications of electrical characteristics and performance on yield and IP or product behavior.
Minimal Travel Required
Language Fluency – English (Written & Verbal)

Preferred Qualifications:

Master’s Degree and of PhD in Circuit Design, Electrical Engineering or related technical field
Strong candidates will have wide experience in functional test engineering including development, transfer of test programs across tester platforms.
Previous experience of Product or IP validation processes and requirements.
He/ she will have a solid background in multiple test platforms (e.g. Advantest / Teradyne) and software languages (e.g. Perl, Python, C/C++).
Deep knowledge in digital CMOS, analog circuit and test structure design, characterization, test/debug, yield enhancement.
Excellent verbal and written communication skills. Strong interpersonal skills and ability to work effectively within a global cross-functional team environment.
Strong knowledge of semiconductor processing and process integration, test chips and test structures for yield limiter determination, improvement and reliability.
Strong knowledge of Advantest 93000 test system, C/C++ programming and Perl scripting skills.
Strong Memory (single, dual and two port SRAM) and Logic (Scan, ATPG) IP knowledge.
Strong knowledge of SQL scripting and JMP data analysis tools.
Strong knowledge of Design for Test capabilities for Logic, Memory and Analog test.
Strong interpersonal skills and ability to work effectively within a global cross-functional team environment. – Project management, peer leadership and mentoring skills.

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To view the job application please visit gfoundries.taleo.net.