FPGA Logic Design Engineer

Website Synopsys
Job Description and Requirements
We are looking for candidate who has an experience in Hardware/Software applications development is interested in defining, design, develop and maintain Hardware/Software based solutions for our FPGA based emulation products. Looking for someone who is excited about the daily technical and human challenges, self-motivated, pro-active, responsive, persistent, exceptional in problem solving.
The candidate will be responsible for:
- Definition, development, validation, and deployment of HW based solutions for our emulation/Prototype platforms in multiple vertical markets.
- Maintain a close interaction with customers, field support, R&D, Marketing, and Sales teams in supporting HW solutions with ZeBu/HAPS platforms.
- Alpha/beta customer rollout and support of HW based solutions to our worldwide customers.
Requirements
- BS/MS/PhD in Electrical, Electronic, Computer Engineering or Science, or related areas
- 6+ years’ relevant logic design and development experience in ASIC/FPGA designs targeted for full SOC applications.
- Work related experience on two or more protocols like Ethernet, PCI Express, SATA, SAS, USB an essential requirement.
- Strong RTL design background with Xilinx FPGA implementation direct experience with minimum 5 years of coding and Xilinx FPGA implementation.
- Good understanding of RTL, testbench, synthesis, mapping RTL to Xilinx FPGA based platform, Unix/Linux development environment.
- Good understanding of synthesis and timing analysis concepts
- Excellent knowledge on FPGA prototyping is essential.
- Experience in development/validation of HW/SW Emulation solutions is a plus.
- Experience with Xilinx transceivers is a big plus.
- Excellent knowledge on programming languages C/C++/ System Verilog/Verilog/Perl/Python/TC is a plus.
- Experience on Advanced functional SoC verification, UVM is a plus.
- Excellent communication skills are required.
Apply for job
To view the job application please visit sjobs.brassring.com.
IP Lifecycle Management for Chiplet-Based SoCs