- Generate test cases to run through emulation and prototype system software tools, find the issue and work with R&D to resolve the issue.
- Write the test plan with different parameters for import, synthesize, partition and P&R modules to cover the software flow.
- Able to download the bin file to FPGA prototype hardware and doing the runtime testing with different runtime setup to cover the runtime software tool.
- Familiar with Xilinx Vivado tool for Synthesize and for P&R
- Familiar with or used the Veriolg, SystemVerilog language and VHDL is a plus.
- Good scripting skills with tck/tcl is a basic and with perl is a plus.
- Good experience using Verdi to debugging RTL and find the issue from waveform.
- Familiar with Linux OS commands and environment.
- Maintains project documentation, testing results and bugs tracking system is a must.
- Good communication skills are important.
- May need to go to customer site to reproduce the issue for R&D and re-create the small test case for remote R&D.
- Minimum of BS or BS and has 1 to 3 years’ experience.
- Working knowledge of Xilinx FPGA, include Vivado synthesize and P&R.
- Experience in Verilog or VHDL and System Verilog is a plus.
- Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project
- Strong software and hardware debugging capability.
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