Formal Verification Engineer

You will join a small, wide-ranging and dedicated formal verification team, working with the design and verification teams to deliver blocks for our next generation GPUs.

Our team collaborates closely with our designers across several design centres who are working on the development of new GPU designs.

The team also collaborates with other formal engineers across Arm to develop methodologies and share technical knowledge. We also work closely with our industry partners in EDA

About the role

We are looking for an experienced formal verification engineer to join a fast-growing team. You will be key to shaping and developing how formal verification is deployed across projects and teams, working with colleagues in our offices across Europe, and the wider formal verification community across Arm.

Become a member of a verification group aiming at promoting, developing and supporting advanced formal verification techniques, your role day-to-day will include building formal verification environments for critical areas of the GPU design; supporting usage of formal tools with design and verification teams.

As a formal champion you will mentor engineers in formal verification, developing their talents and understanding of formal techniques and application of formal methodologies.

Develop new formal methodologies to be rolled out to the wider design and verification teams and investigate new capabilities based on formal. Interact and co-operate with EDA vendors, to develop new features, improve performance and make sure their tools meet the needs of the GPU team.

There may also be opportunities to present new techniques and applications to GPU users wider Arm community and at industry conferences.

Essential Attributes

• Experience of architecting and implementing formal verification environments for complex IP/module level designs.
• Experience of property-based model-checking, practical experience of SystemVerilog Assertions (SVA) or Property Specification Language (PSL),
• with an industry leading formal tool (e.g. Cadence JasperGold, Siemens EDA QuestaFormal, Synopsys VC-Formal or OneSpin 360 DV-Verify).
• Ability to quickly understand and apply complex specification details.
• Commit to solve varied and sophisticated technical challenges.
• In-depth knowledge and enthusiasm with skills to drive adoption of new techniques and methodologies with a focus on quality and efficiency.
• Strong communication skills and ability to work well as part of a team.
• Proven track record of technically owning, implementing and driving the verification process from test plan creation to verification sign-off through individual contribution and delivery through others.

Desirable Attributes

• Experience of formal sequential equivalence checking with a leading industry tool (eg. Synopsys Hector or Mentor Calypto SLEC) or theorem-proving techniques.
• Knowledge in Python, Perl or TCL scripting languages.
• CPU or GPU verification experience.
• Experience working and communicating with remote design centres.