Job Responsibilities and Qualifications:
1. Proficient or familiar with front-end tool flow, such as synthesis, Formal, DFT, etc.
2. Familiar with EZECO, capable of independently performing Formal debugging and problem solving.
3. Familiar with APR flow of chip physical design, RTL, Verilog, formal verification tools.
4. Master’s degree or higher in integrated circuit, electronics, or communication related field.
5. Bachelor’s degree can also be considered if the candidate has work experience in IC design field, ASIC verification, or functional ECO.
6. This position requires frequent business travel.
Taiwan, Shanghai, Beijing, Shenzhen
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