SIC 2020 Forum 800x100 1

Engineer Trainee

Engineer Trainee
by Admin on 06-23-2020 at 10:06 am

  • Full Time
  • US

Website SmartDV

  • B.E or MTech from reputed university with 0-2 years experience.
  • Strong understanding of Digital design
  • Working experience with Verilog or VHDL or SystemVerilog
  • Experience in writing C or C++
  • Understanding of OOPS.
  • Knowledge of Perl or Python or TCL scripting languages
  • Very good academic track record
Apply for job

To view the job application please visit