- The charter of the CoreBSP-DDR SW System team is to ensure that the end-product qualifies the defined acceptance criteria for DDR by meeting stability, Power and Performance Goals .
- The team is looking for a candidate who has strong understating of system level test methodologies and run validations on mobile systems.
- The position involves Understanding of SOC Architecture and DDR SW Systems, identifying and debugging DDR systems issues ( memory corruptions, Memory Lock-ups, Bit flips, memory leaks etc..)reported by memory validation and also running system level validations tests.
- The engineer would have opportunity to interact with different SW & HW teams to understand DDR systems.
- This position gives an exposure to understand various quality stages from product development to commercial launch of the product.
- Strong in C Programming and Boot loaders
- Good analytical / problem solving / sound reasoning skills
- Good understanding about any CPU architecture
- Good understanding SOC systems knowledge level tests validation methodologies.
- Good understanding in working android environment.
- Experience of core BSP driver level development and debug.
- Good understating of working debug tools like JTAG/TRACE.
- Working knowledge with any serial protocols
- Awareness of RTOS operating system fundamentals / processor architecture /embedded system and microprocessor concepts.
- Understanding of DRAM technologies(LPDDR & PCDDR) and working on DRAM interface signal analysis is big plus
The candidate is expected to be self-driven to quickly get up to speed on various aspects of DDR validation & flexible to take-up tasks as per the project needs.
Apply for job
To view the job application please visit mobiveil.com.