DV Engineer (SV / UVM)

Requirements

• 6+ years of experience working in SoC / IP / Block/ Sub system/ level verification
• Strong experience in SV UVM or any methodology.
• Understand current verification methodologies for complex ASIC designs.
• Experience implementing directed and random test cases.
• Experience in creating test plan, writing test cases and debugging logic.
• Experience with mixed RTL/DV, assertion, formal verification and code coverage.
• Ability to rapidly review and understand complex RTL written in Verilog
• Knowledge of protocols such as Ethernet, PCI-Express, USB, MIPI, AXI, Rapid IO, NVM Express and LPDDR2/LPDDR3 is a plus
• Strong analytical skills with attention to detail
• Fluent in Verilog, Linux/Unix and scripting languages
• Fluent in and System Verilog and Specman
• Excellent written & verbal communications skills.