DTP Engineer

Job Responsibilities

At the beginning of new module research, IC design engineers and R&D engineers would cooperate closely with customers. Therefore, once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time.

In TSMC, you could be exposed to the most advanced module technologies, provide solutions to partners in global IC design eco-system, and ensure the competitiveness in power, performance, and area.

【Physical Designer】

The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps, which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. Candidate will work in a talented team to design advanced chips, using cutting-edge process nodes while meeting high standard design requirements.

【Standard Cell Engineer】

1. Path finding of library characterization for leading-edge technology nodes
2. Support industrial standard library kits generation and QC
3. In-house library generation flow and/or utility development
4. RC parasitic extraction analysis and APR related analysis

【Layout Engineer】

1. IC layout for advanced technology (Std. cell/Memory/AMS/IO)
2. Layout structure development for new technology
3. Pathfinding for new technology development
4. Customer engagement and layout support
5. Design and technology co-optimization (DTCO)
6. AI and automation for layout and physical design

【3DIC Eng.】

GPIO/ESD design, 3DIC/2.5DIC interface-IO design, and Si validation.

【System and Chip Design Solutions Development】

Detailed Job Description

【FE design & DFT】

1. Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG)
2. Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting, etc.
3. Technology benchmarking for PPA evaluation of the advanced nodes
4. DTCO (Design & Technology Co-Optimization) pathfinding and developmen

【SRAM Eng.】

1. SRAM design in 7nm/5nm/3nm for mobile, high-performance computing, IoT, and automotive applications.
2. RRAM/MRAM, emerging memory development
3. In memory computing research and development

【Design Flow/Methodology】

1.  Advanced technology process design kits (PDK) and tech files (e.g., DRC, LVS, RC) development and technical support
2. Advanced technology design development flow development and technical support
3. Automation program development to support design kits and flow development productivity/quality

Job Qualifications

1. Master’s degree in Electrical Engineer or Computer Science
2. Good spoken and written English
3. Good understanding of place and route flow
4. Good interpersonal and communication skills
5. Self-motivated and excellent team spirit