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Digital Verification Engr, Senior

Digital Verification Engr, Senior
by Admin on 08-10-2022 at 4:09 pm

Website Synopsys

Seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team, and will be involved in verifying current and next generation PAM-based SerDes products. The position offers an excellent opportunity to work with a skilled team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

Responsibilities of this job include

  • Writing modular constrained-random Verilog and SystemVerilog testbenches
  • Performing functional coverage
  • Assertion coverage and code coverage
  • Creating and tracking test-plans
  • Evaluating failure cases and running gate-level simulations

Key Qualifications

  • BSEE or MSEE with 5+ years of digital verification experience in the industry
  • Must have hands-on experience in writing complex testcases in Verilog and SystemVerilog
  • Must have familiarity with code quality metrics

Preferred Experience / Knowledge

  • High-speed digital & mixed-signal design & verification
  • Asynchronous clock domain crossing
  • Familiar with UVM methodology and verification using VCS/Verdi
  • Good organization and communication skills
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To view the job application please visit sjobs.brassring.com.

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