Digital IC Design/Verification engineer

Description

1. DDR/PCIe/UCIe configuration, integration and verification.

2. Interact with external IP vendors/customers to resolve integration /implementation issues.

3. Co-work with customers for chip bring-up.

Requirements

1. At least 2 years of IC front-end design industry experience.

2. Solid digital design/verification skills (Verilog coding, RTL/netlist simulation, SystemVerilog, UVM)

3. Familiar with implementation skills ( LINT/SDC/CDC, synthesis, formal, STA).

4. Familiar with DDR/PCIe/UCIe specification and protocol.

5. Working experience in DDR/PCIe/UCIe subsystem integration/UVM verification

6. SoC verification experience with UVM is plus.

7. Programming skill in Perl scripting.

8. Team player, fluent in English (verbal and written)

9. Excellent interpersonal/communication skills for technical lead position.