Digital Designer – Senior

What you’ll do

• Micro architecture and hardware level definitions
• RTL design in SystemVerilog/Verilog
• Synthesis, static timing analysis and timing closure
• Development of verification for functional blocks and systems
• Lead, plan, and coordinate tasks with team members on design of more complex design blocks and features
• Work with technical and project managers to create development plans and schedules
• Debug and support block and system level simulations and models
• Linting, equivalence checking, clock domain crossing (cdc) analysis
• Debug silicon in lab on block and system level issues
• Cross domain collaborations with other AW teams can include: systems, analog, physical design, SoC, FW/SW, marketing, project management

What You’ll Need

• Bachelors or Masters Degree in Electrical or Computer Engineering
• Experience with RTL coding in SystemVerilog, and Verilog
• Experience with industry standard IC design tools (synthesis, simulation, equivalence checking, static timing analysis)
• Knowledge of scripting, Linux/Unix environment
• Tools/Languages: SystemVerilog/Verilog, Python, Perl, C/C++, GNU Make
• Solid understanding of ASIC/IC design flow
• Design for verification experience or understanding (constrained-random verification with UVM, assertion-based design strategies, code coverage, functional coverage, test planning, etc.) would be an asset

“Hybrid work environment”

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

• Great compensation package
• Health Insurance
• Retirement Savings
• Paid time off