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DFT Engineer

DFT Engineer
by Admin on 01-10-2023 at 2:11 pm

Website Agnisys

Skill Set Requirements:

  • Full-chip DFT working experience with multiple design Tape Outs
    Block level and Chip level SCAN insertion, DRC, Coverage Analysis, and improvements.
  • Expertise in Scan Compression (EDT/OPMISR+), MBIST, BSCAN, ATPG implementation, and verification.
  • Hands-on Experience with industry standard DFT EDA tools & flows (Tessent, Synopsys, Cadence)
  • Good Knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments & LEC.
  • Excellent problem-solving and debugging skills. Proactive in nature.
  • Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
  • Leading junior teams, Mentoring/Training, and Project leadership.
  • Excellent Customer interaction, Communication, and Teamwork skills

Skills & Experience

ATPG (at-speed & stuck-at), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT), Design Rule Checking (DRC), Formal Verification, Gate Level Simulation, Hardware Description Language (HDL), Test Pattern Generators

Job Types: Full-time, Regular / Permanent

Ability to commute/relocate:

Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (Required)

Education: Bachelor’s (Preferred)

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To view the job application please visit

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