Design Verification Engineer H/F

Arteris enables engineering and design teams at the world’s most transformative companies to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve already come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

We are looking for a  Design Verification Engineer to join our teams and work on the most advanced SoC assembly and HSI flows. In this role, you will directly influence the development environment, the architecture, the verification, and everything in-between.

Responsibilities:

• Define, document, develop, and execute simulation-based verification tests for Arteris’ Register Bank Compiler tool, compatible with major RTL simulators (Cadence, Synopsys, Siemens).
• Define, document, develop, and execute Python-based validation tests for qualifying Register tool collaterals (IP-XACT, C Header files, Documentation).
• Maintain and enhance tests in the continuous integration flow, refine metrics, and increase automation.
• Contribute to improving processes, methodologies, and metrics.
• Use modern tools for documentation, specification, task, and project tracking (Confluence, Jira).
• Collaborate with developers to identify EDA-specific testing needs and scenarios.
• Participate in code reviews and unit testing to ensure code quality.

Requirements:

• 7+ years of experience as an RTL verification engineer.
• Strong expertise in the UVM framework.
• Knowledge of RTL design languages (VHDL, Verilog, SystemVerilog).
• Proficiency in Python scripting.
• Knowledge of IP-XACT, C-HAL, and equivalence checking tools is a plus.
• Strong communication skills in English, written and verbal.
• Curious, autonomous, rigorous, delivery-oriented, with a commitment to quality.

Education:

• Engineering degree in computer science, electronics, or related field.

Languages:

• Fluent English required.
• French proficiency is a plus.

Salary:

• €60K–75K per year, depending on experience.

About Arteris:

Arteris is a leading provider of system IP for accelerating SoC development in modern electronic systems. Its NoC interconnect IP and SoC integration automation technology improve product performance, reduce power consumption, and shorten time to market.

With over 250 employees worldwide and headquarters in Silicon Valley, Arteris drives SoC innovation for both startups and global tech leaders.

➡ Learn more: www.arteris.com