Design Verification Engineer

Job Title: Design Verification Engineer
Location: Campbell, CA USA
Organization: Arteris IP
Date posted: 2020-01-14

Do you want to contribute to the backbone of the some of the world’s most popular SoCs?

You will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You’ll create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Responsibilities:

• Advanced UVM based test bench development and debugging
• Defining, documenting, developing and executing RTL verification test/coverage at system level
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure

Experience, Requirements and Qualifications:

• 1 or more years of design and verification experience and a plus in interconnect verification experience
• Experience with Cadence, Synopsys, Mentor logic simulators
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript

Education: 

• BS degree or higher in Engineering or Computer Science