Design Verification Engineer

Job Description:  Architect, define and develop advanced UVM based test benches using System-Verilog, Java-Script and JSON tools. Debug test-benches using EDA interactive tools. Define, document, develop and execute design verification test plan. Define, develop and closure on functional and code coverages. Triaging Regressions, debugging RTL designs in Verilog and System Verilog. Improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure.

Requirements: Requires Master’s degree in Computer Engineering, Electrical Engineering, Computer Science or related field. Requires 5 years of experience which must include some experience in the following skills: Architect, define and develop complex SOC-level test-benches to perform functional verification of SoC (System on Chip) embedded RISC/DSP processors, communications, networking ASIC hardware (interconnect) at IP, sub-system, SoC and system architecture level for server processors and applications; Verify RTL design using object-oriented verification language called System-Verilog in a UVM-based verification environment; EDA (Electronic Design Automation) tools to debug regression and simulation issues to improve quality of the ASIC design; Automated test patterns/sequence generation using scripting language (Perl); Develop test-plans, functional coverage and subsequent coverage analysis to ensure RTL design is thoroughly verified; and Computer architecture and cache-coherency in multi-processor systems.

To Apply Send Resume to: HR Recruiting, Arteris, 595 Millich Dr., Ste 200, Campbell CA 95008