Design Verification Cache Coherency Specialist

Do you want to contribute to the backbone of some of the world’s most popular SoCs?

As a Design Verification Cache Coherency Specialist at Arteris, you will have an exceptional opportunity to be part of a verification team working on highly configurable interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine.   Your co-workers will be an experienced team of industry experts that love what they do.

Requirements:

• BS/MS in EE, CE, CS; or in another engineering/technical discipline with equivalent experience.
• Minimum 8 years of design verification experience verifying complex SoCs/ASICs at System Level.
• Cache Coherency experience is required – L1/L2 cache coherency.
• Proficiency with Verilog/VHDL and scripting languages such as Python, TCL, Perl, Ruby, etc.
• Experience developing test plans.
• Strong experience developing verification infrastructure using UVM.
• Familiarity with the use of third-party VIPs/AIPs
• Team player with strong communication skills, and ability to work independently on the verification of a portion of the design.
• Prior Micro-processor (CPU) and/ and memory sub-system verification experience.

Nice-to-Have:

• Familiarity with interfaces like AXI, OCP, PCIE etc.
• Formal verification experience writing properties and stimulus generation.
• Prior start-up experience.