- Implement the RTL to GDS design flow.
- Complete the chip/complex block timing constraint, logic synthesis, STA, test logic circuit design.
- Complete the chip/complex block P&R, power analysis, physical verification, low power check, ESD check.
- Develop/maintain the physical design implementation related flow.
- Provide technical support for customer/FAE/FEE/sales.
- Master’s or above degree in EE/CS related majors, 1-3 years working experience.
- Familiar with the main physical design EDA tools.
- Strong scripting abilities in TCL/PERL.
- Single or multiple experiences on design implementation from RTL to GDS, chip level testing, ASIC coding and simulation, ASIC physical layout, IC manufacture and process.
- Ability to help and lead Junior Engineer to solve problem.
- Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.
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