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Design for Test Engineer

Design for Test Engineer
by Admin on 09-26-2022 at 2:03 pm

Website Syntiant

Member of Technical Staff position is for experienced SoC verification engineer responsible for pre-silicon RTL verification at the block and top-level SoC.

  • Expertise in HDL languages, Verilog and SystemVerilog, SystemC is desired

  • Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy

  • Solid verification skills in problem solving and debugging

  • Programming experience in C/C++ as well as Python

  • Exposure to UVM is desired

  • Work on HW/SW emulation platforms

Minimum qualifications:

  • MS degree in EE, 5+ years relevant experience in SoC verification

*To apply, send your PDF resume to join (at) syntiant (dot) com with the subject line “Design for Test Engineer”.

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