Design for Test Engineer
Member of Technical Staff position is for experienced SoC verification engineer responsible for pre-silicon RTL verification at the block and top-level SoC.
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Expertise in HDL languages, Verilog and SystemVerilog, SystemC is desired
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Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
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Solid verification skills in problem solving and debugging
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Programming experience in C/C++ as well as Python
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Exposure to UVM is desired
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Work on HW/SW emulation platforms
Minimum qualifications:
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MS degree in EE, 5+ years relevant experience in SoC verification
*To apply, send your PDF resume to join (at) syntiant (dot) com with the subject line “Design for Test Engineer”.
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