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Design Engineering Group Director

Design Engineering Group Director
by Admin on 03-27-2023 at 4:08 pm

Website Cadence

Job Description

Leading the development of FPGA ready SoC Reference Designs for Embedded and Application class Tensilica CPUs using your experience in SoC architecture, FPGA systems bring-up and System Validation of such designs for use with SW/FW bring-up, OS bring-up, benchmark exploration, functional validation etc. and be primary vehicle for software development and analysis.

Leading the development and bring-up of the functional safety (FUSA) systems and infrastructure for the Tensilica CPU cores working with the resident FuSa experts @Cadence.

Interact with other leaders and teams within the division, including marketing, silicon engineering, firmware/algorithms, applications engineering, and sales, in defining and developing and delivering compelling products.

Duties and Responsibilities:

This role would be responsible for directly managing and leading a small, global cross-discipline team to define, implement, prototype, and eventually deliver working FPGA hardware systems based on industry standard boards that enable SDK development for Tensilica CPUs.  The candidate will also manage the FuSa systems development and HW infrastructure verification/validation and bring-up of Tensilica CPU cores, while working with resident FuSa experts @Cadence to support the required design safety analysis.

Job Requirements:

  • Deep knowledge of CPU and/or SOC architecture and development
  • Experience in FPGA & ASIC design flow with proficiency in using ASIC & FPGA design tools from RTL to GDS
  • Experience in FuSa per ISO26262 for certification up to ASIL level D
  • Strong track record in understanding design management and processes, especially in HW and System development.
  • Requires interfacing with internal global teams
  • Proven experience in leading and managing global teams
  • Strong managerial, leadership, and interpersonal skills
  • Master’s or Doctorate degree in Electrical Engineering, Computer Science, or related field and/or 15+ years of relevant SoC design experience.

The annual salary range for San Jose, CA is $ 183,400 to $340,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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To view the job application please visit cadence.wd1.myworkdayjobs.com.

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