Design Engineering Architect

Job Description:

• Proficient in Verilog coding and RTL design, data path designs,
• Knowledge of RTL checks ex- LINT, SDC, CDC
• Familiar with synthesis flow and timing constraints
• Experience in writing Verilog testbench and running simulations.
• Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/Display

Nature of work:

• The Candidate will be responsible for the design and implementation of high-speed SerDes PHY at the cutting edge nodes.
• Responsibilities include the architecture of high-speed SerDes IP, design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.
• Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits

Requirement:

• The Candidate is expected to have a good understanding of the digital design flow.
• Proficient in Verilog coding
• Proficient in high-speed design, RTL coding, datapath designs, working at GHz frequencies.