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Design Architect

Design Architect
by Admin on 06-09-2020 at 10:34 am

  • Full Time
  • SAN JOSE
  • Applications have closed

Website Cadence

Position Summary

Cadence Design Systems is looking for a PHY Architect to participate in the PHY Architecture development for modular, scalable, high-performance, low-power, next-generation Memory Interfaces on latest process technologies.

 Responsibilities

  • Defines, Documents and Designs PHY Architectures for High-Performance/Low-Power Memory Interfaces supporting multiple SOC applications.
  • Architecture study of DDR, GDDR, LPDDR and HBM memory subsystems.
  • Work with a team to define PHY RTL & timing constraints and provides guidance to Design verification and Physical design.
  • System Modeling, Architecture, Design and Development of high performance, low power IO PHY meeting latest Memory Industry Standards for LPDDR, DDR Or Proprietary On-Package Interconnects standards.
  • Collaborate across functional teams – Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best In Class Power, Performance and Area metrics.
  • Collaborate with SoC integration teams on PHY level requirement and integration issues.
  • Mentor and develop technical leadership pipeline.

Requirements

  • Experience in PHY Architecture, Circuit/Logic Micro-Architecture definition of High Speed Memory Interfaces example DDR, LPDDR, GDDR, or On-Package Interconnect IO interfaces, Ultra Low Power Die-to-Die IO. Design achieved production in high volume and extensive exposure on post-silicon debug and Hardware and Firmware based PHY training algorithms
  • Hands-On Experience in high speed design building blocks for High Speed Interfaces, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC
  • Understanding of LPDDR/DDR/GDDR JEDEC specifications and related Memory Interface Protocols
  • Knowledge of DFI based Memory Sub-systems, Power/Performance optimization and Package/Platform trade-offs is required.
  • PHY Architecture knowledge needs to span multiple domains (Analog, Digital, Platform Electricals, etc.)
  • Understanding of design for yield and exposure to production challenges in latest technology process nodes.
  • Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training and Architecture specification documentation.
  • Strong written, oral communication and presentation skills
  • Bachelor of Science degree with at least 15+ years additional experience, or a Master of Science degree with at least 10+ years additional experience, in Computer Science, Computer Engineering, or Electrical Engineering.
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