CXL/PCIe Architect
Website Semidynamics
Description
We’re looking for a strong candidate with expertise in PCIe and CXL2.0/3.0 to architect and design our CXL-to-CHI bridge. Our cores use the AMBA-CHI protocol for coherency and we want the CXL.mem and CXL.cache protocols to allow our IP to seamlessly interoprate with CXL-enabled hosts. You will be architecting the bridge and also writing the RTL for it, so RTL skills are also required!
Requirements
– PCie
– CXL
– RTL (verilog/vhdl)
– Master or PhD
– C++ and scripting
– CXL
– RTL (verilog/vhdl)
– Master or PhD
– C++ and scripting
Apply for job
To view the job application please visit semidynamics.com.
IP Lifecycle Management for Chiplet-Based SoCs