Lead Application Engineer

We are looking for a talented Simulation Engineer to join our team . The ideal candidate will have six years’ experience working on Cadence EDA tools like Sigrity and Allegro.

The engineer is expected to focus on.

1. Package/PCB Model extraction and design Analysis.

2. System level Simulation modeling, characterization and simulation from PCB, package and IC.

3. Co-simulation flow application.

4. Engages interest and participation of partner and has a collaborative approach to working with partner.

5. Work closely and interface with various teams.

Requirements:

1.Experience in package substrate layout, PCB board level layout.

2.Strong fundamentals of transmission lines, RF, EM theory.

3.Experience with SERDES characterizations and channel equalizations, such as PCI-E,USB, MIPI, HDMI, SATA, SAS 56Gbps-PAM4.

4.Experience with memory characterizations and channel equalizations, such as DDR3/4, LPDDR3/4 and HBM.

5.Familer in using EM simulations tools.

6.A plus for Good Command of written and oral in English.

This is a unique opportunity to join a creative team and work with talented colleagues around the world.