Lead Application Engineer

To provide key technical support and solution deployment in system design and verification field. Collaborate with business, engineering, and other internal teams to provide customers promising solution by Cadence Verification Tools. To demonstrate strong ability and to be hands-on in RTL comprehension, System Verification, Embedded System bringup, Performance analysis. Assist product marketing and engineering team in pre and post sales situations with high quality delivery and endorsed by customers.

Position Requirements:

Bachelor’s/Master’s degree in engineering.  2+ years’ experience in Digital Design or SOC verification, or Embedded SW/FW or Semiconductor design. Ability to understand and articulate technical issues with precise system perspective, from SW to module level design. Verification related language in Verilog/Systemverilog/C/SystemC, one of them shall be expert level. Also familiar with scripting including Python/Perl/Makefile/TCL/Shell Fluent in English, effective communication and proper softskill to priority dynamic request from customer Self-motivated, eager to learn, enjoy cross-site, cross-nation, cross-culture collaboration.

Following Qualification are Big plus:

UVM and DV related achievement, VIP adoption/closure. Assertion Based verification included. Virtual platform related architectural exploration and SW-HW co-development. Digital design expertise from specification till mass production, SOC integration in highly competitive market. Embedded SW bringup of Multimedia/ Networking/ Automotive system. Emulator, FPGA handson experiences Protocol hands experiences of DDR/FLASH/PCIE/USB/HDMI/MIPI Power Performance Area exploration in model/RTL/Netlist stage to achieve excellence.