At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As a member of the Silicon Engineering Team, the Physical Design Engineer contributes to the implementation of advanced node SoC designs from netlist to tape out.
Must be able to obtain and maintain a Department of Defense classified clearance.
Skills include floorplanning, clock design, place and route, static timing analysis, and physical verification. Minimum 5 years experience with Cadence Digital Implementation tools or equivalent (Innovus, Tempus, Voltus, Pegasus). Project leadership experience a plus. Minimum BSEE, MSEE preferred.
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