At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Analog/Mixed Signal Design Engineer will be responsible for the design and development of analog/mixed signal SerDes macros from initial concept and specification, through final verification and conformance to customer requirements.
BSEE is required [MSEE/PhD preferred].
Ideally, candidate’s background should include some experience in high speed SerDes designs in low geometry CMOS processes.
Working knowledge of a set of common SerDes standards and their electrical requirements.
Deep design knowledge/experience in one or more of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators would be a plus.
Candidate must be able to own a block or set of blocks for analog SerDes IC design.
Candidate should have good problem-solving skills, analog aptitude, communication skills, and the ability to work cooperatively in a team environment.
Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification (Cadence tool experience, lab test experience, and design experience at >10Gbps and in <40nm technologies are a plus).
Candidate must have a positive attitude and a willingness to learn.
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