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https://www.asiafinancial.com/curbs-on-asml-to-stop-use-of-advanced-chips-by-china-military: In January, ASML said it expects China sales to remain “solid” in 2024 after an exceptional 2023. The company…
Are you passionate about microprocessor architecture? We are your match! As a Senior Die to Die Communication Design Engineer, you will be at the heart of the design and development of the Die to Die solutions for our semiconductor portfolio. You will work within the Die to Die Communication Design Team and work closely with other teams’ highly skilled engineers to guarantee a successful tape-out and bring-up, enabling the future through Chiplets.
What we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)
Requirements
Master or PhD
English C1
Industrial experience +8 years
Knowledge of die-to-die standards (e.g. UCIe or XSR)
Experience with signal conditioning
Proficiency in RTL design using Verilog or VHDL
Knowledge of scripting languages (Python, Perl, Bash, TCL)
Experience with EDA tools and synthesis
Experience with Timing and Timings Constraints
Knowledge of revision control methodology and tools ( git, svn)
Strong problem-solving skills and attention to detail
https://www.asiafinancial.com/curbs-on-asml-to-stop-use-of-advanced-chips-by-china-military: In January, ASML said it expects China sales to remain “solid” in 2024 after an exceptional 2023. The company…
Has ASML Reached the Great Wall of China