This position is a DFT and DFD RTL Design engineer inside the Atom CPU DFX (Design For Testing and Design For Debug) team, which is part of Atom CPU RTL organization. As a DFT engineer, you are part of the Atom CPU team where you can make significant contribution to make future Atom CPUs meeting strict DFT and DFD requirements of a variety of market segments.
Your close collaboration with other pre-silicon and post-silicon teams leads to complete solutions to hit our test and debug goals for future Atom CPUs. On our talented team, you will be able to expand your technical breadth and depth related to leading-edge DFT/DFD design. You will also have a chance to work on the advanced functional safety features for Atom CPU.
- Write RTL for DFT and DFD block including TAP controller, debug controller.
- Help to drive presilicon validation to ensure the developed DFT/DFD features are covered by presilicon validation tests.
- Work closely with validation engineers to debug validation tests in both RTL model and netlist model.
- Work with post silicon team to enable DFT and DFT features in silicon and drive silicon debug.
- Solid RTL coding skills and good understanding on DFD and DFT architectures.
- Good understanding on general CPU architecture.
- Solid debug capability.
- Knowledge on IEEE standards related to JTAG.
- Experience on scan ATPG and memory BIST are preferred but not required.
- MS or PhD in Electrical or Computer Engineering.
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To view the job application please visit jobs.intel.com.