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ASIC Physical Design, Staff Engineer

ASIC Physical Design, Staff Engineer
by Admin on 03-12-2024 at 4:10 pm

Website Synopsys

Years of Exp:

5 – 9 yrs.

Job Description

STA for High Performance Designs like DDR/LPDDR,UCIE,HBM and SOC.
Responsible for timing closure activities for High performance IPs
Close the design to meet timing , power and area requirements.
Implement engineering change orders (ECO) to rectify functional bugs and timing issues.

Ensure qualiity and efficiency of RTL2GDS implementation process.
Strong Automation background in Python, Perl , TCL, Shell scripting.
Good to have hands on experience in Physical Design, STA and similar domains.

Skill Set

  • Good knowledge and hands-on experience in static timing analysis (closing timing at chip level)
  • Good understanding of timing constraints.
  • Should have experience inhandling asynchronous timing , multiple corner timing closure
  • Familiar with PT , PTECO and DMSA
  • Proficient in scripting languages (Tcl and Python).
  • Ability to communicate effectively with multiple global cross-functional teams.
  • Effective presentation skills.
Apply for job

To view the job application please visit careers.synopsys.com.

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