Job Description and Requirements
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Senior ASIC Physical Design Engineer
We’re looking for a Senior ASIC Design Engineer to join our team.
In this role, you will be part of the global DDR engineering team performing digital implementation of DDR and HBM PHYs in to various technology nodes. You will contribute as a Senior Member of a design team, or as a Project Design Lead working with both internal and external design teams, giving valuable feedback to improve the quality of the overall Synopsys IP.
- Performs in a project leadership role
- Demonstrates good analysis and problem-solving skills and contributes to complex aspects of a project
- Ability to keep composure during crises and comfortably handle risks and uncertainty
- A strong desire to learn and explore new techniques and technologies
- Frequently networks with senior internal and external personnel in own area of expertise
- Guides more junior peers with aspects of their job
- Typically requires a minimum of 7+ years of related experience
- Full understanding of specialization area plus working knowledge of multiple related areas
- Prior knowledge and experience with state of the art CAD tools (DC, PT, ICC2, ICV) and technologies (FinFet) is required
- Experience with Physical Verification (DRC, LVS, Antenna, etc) error analysis and fixing
- Ability to independently resolve a wide range of issues in creative ways on a regular basis
- Strong communication skills, verbal and written, and awareness of project management issues