In this role it is important to acquire competencies an all backend phases, like floorplan, power plan and timing constraints and closure, as well as to ensure clean physical verification, track and ensure on-time incoming and outgoing deliveries.
- Work in all backend flow stages: Synthesis, Place & Route, Timing Analysis and Physical Verification
- Work with senior team members
- Report on project execution progress
- Provide technical feedback to design teams and management.
- Degree in electrical engineering or computer science
- Experience and interest in ASIC physical implementation and Place & Route flows.
- Knowledge of scripting and programing languages (ex: TCL, Unix Shell, Python)
- Verbal and written fluency in the English language.
- Knowledge of industry standard data file formats: Verilog, GDSII, LEF, DEF, SDF, LIB
- Practical experience with Synopsys P&R tool set: Design Compiler, IC Compiler(2), Prime Time, IC Validator
- Knowledge in C/C++