ASIC Digital Design Engr, Sr II

Job Responsibilities:

• Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc.
• May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity modules in the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI
• Creates deliverables which do not require close review or supervision by a Senior Technical Lead.
• May learn to do technical review of TE Code of small complexity.
• The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment, at least for small/ medium complexity features of the protocol/ product specs.
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

• Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.
• Knowledge of one or more of protocols: Ethernet/USB/AMBA (AMBA2, AXI)/ MIPI
• Hands on experience with creating detailed design of certain simple components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM.
• Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.