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ASIC Digital Design Engineer, II ‎

ASIC Digital Design Engineer, II ‎
by Admin on 08-14-2023 at 4:10 pm

Website Synopsys

Job Description and Requirements

  • The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India.
  • The position offers learning and growth opportunities. This is a Technical Individual Contributor role.
  • The role offers opportunities to work in a collaborative environment on complex IP Cores.
  • The role calls for IP Verification using latest methodologies, tools and flows.

Job Description

The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He/She will be expected to specify and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. He/She will work closely with RTL designers and be part of a global team of professional Verification Engineers.

Will be working on the next generation MIPI protocols for commercial and Automotive applications.

Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding, debugging, FC coding, testing, meeting quality metric goals and regression management.


  • BS in EE with at least 3 years of relevant experience or MS with 1+ years of relevant experience in the verification of IP cores and/or SOC RTL designs.
  • Must have experience in developing HVL (System Verilog) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.
  • Must have exceptional HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
  • Expertise on verification methodologies such as VMM/OVM/UVM/ is required.
  • Working knowledge and experience of one or more of the connectivity protocols such as MIPI UFS/Unipro, M-PHY RMMI, I3C and AMBA is preferred.
  • Familiarity with HDLs such as Verilog and scripting languages such as Perl is highly desired.
  • Exposure to IP design and verification processes including VIP development is an added advantage.
  • There will be sound focus on functional coverage based methodology. Therefore corresponding mindset is a must.
  • Familiarity with scripting language is an added advantage.
  • Familiarity with code review tools, bug reporting tools and repository tools is added advantage.
  • It is essential that the person has good written and oral communication skills and is able to demonstrate good testing, debug, problem solving skills and be self-guided.
Apply for job

To view the job application please visit sjobs.brassring.com.

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