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ASIC DFT Design, Staff Engineer

ASIC DFT Design, Staff Engineer
by Admin on 03-12-2024 at 4:15 pm

Website Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars Artificial Intelligence. The Cloud 5G. The internet of things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. if you share our passion for innovation, we want to meet you.

Our Silicon IP Business is all about integrating more capability’s info an SOC-faster. We offer the worlds broadest portfolio of silicon IP–predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

ASIC Physical Design, Staff Engineer

We’re looking for Senior ASIC DFT Engineer to join our team.

Does this sound like a good role for you?

In this role, candidate will be part of engineering team implementing DDR, HBM, UCIE PHY’s for customer ASICs and SOCs in DDR-HBM-UCIE PHY Hardening service line, which includes front end implementation, physical design, verification, design for test and ATPG. Candidate will contribute as a senior Member of a design team or as Project Design Lead working both internal and external design teams.

Ideal candidate for this role demonstrates excellent technical knowledge, strong communication skills, verbal and written, and awareness of project management issues. keeps composure during crises and can comfortably handle risks and uncertainty. She/he has a strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience with state of the CAD tools (Fusion Compiler, Design compiler, tetramax, VCS, Spyglass) and technologies (FinFet) is required. Customarily exercises independent judgement in selecting methods and techniques to obtain solutions. Performs in the project leadership role. Contributes to complex aspects of a project. determines and develops approach to solutions. Provides regular updates to manager on the project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job. Frequently networks with senior internal and external personal in own area of expertise.

Key Qualification.

Typically, requires a minimum if 5+ years of related experience.

  • Excellent understanding of DFT architectures & methodologies which includes Scan insertion, ATPG, JTAG, SIMS etc.
  • Must have experience in generating scan patterns and coverage statistics for various fault models like stuck at, IDDQ, Transition faults and path delay.
  • Experience in Scan Stuck-At and At-Speed coverage exploration, simulation and debug.
  • Hands on experience in state-of-the-art EDA tools for DFT, design and verification.
  • STA for DFT mode timing constraint development and exploration is a plus.
  • Excellent debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus.
  • Good Communications skills and the ability to effectively work with cross functional teams across geographies are required.
  • Design experience in MBIST, LBIST and Analog DFT is an added advantage.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender sexual orientation gender identity, age, military veteran status, or disability.

Apply for job

To view the job application please visit careers.synopsys.com.

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