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Senior Emulation Verification Engineer

Senior Emulation Verification Engineer
by Daniel Nenni on 09-08-2020 at 6:50 pm

Website ArterisIP

As a Senior Emulation Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Key Responsibilities:

Maintaining hardware emulation system in full operational condition
Defining, documenting, developing and executing emulation process for multiple projects
Integrating hardware emulation system to different software platform
Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
Help improve and refine emulation process, methodology, and metrics
Experience Requirements / Qualifications:

10 or more years of hardware emulation experience and a plus in interconnect verification experience
Strong emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput optimization
Experience using Verilog, VHDL design, System Verilog
Experience with C/C++ and System Verilog, UVM verification environments
Experience writing scripts using Perl, Python, Makefile
Debugging experience using tools like waveform, Verdi, Simvision, Visualizer
Strong communication skills and ability to work as a team
Plus, working with Hycon platform and strong familiarity with ARM CPUs
This opportunity involves high performance, low power designs on a highly visible project
Education Requirements:

MS degree in EE, CS, or equivalent preferred. BS degree minimum.

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To view the job application please visit www.arteris.com.