Job Description and Requirements
- Experience in Analog Mixed-signal layout and verification , experience in high-speed SerDes IPs is a plus
- Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, Advanced strategies.
- Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below.
- Good understanding of basic ESD and latch-up layout design considerations.
- Remote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical skills.
- Excellent written and verbal communication skills in interactions with internal development teams.
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To view the job application please visit sjobs.brassring.com.