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AI RTL Frontend Design Engineer

AI RTL Frontend Design Engineer
by Admin on 04-08-2022 at 11:54 am

Website Flex Logix

Flex Logix is seeking a RTL/Frontend Design Engineer to join our team developing/migrating the RTL of the eFPGA and the next-generation InferX solutions.


  • The candidate must be able to work in the architecture/frontend stage of silicon development: specification, coding, some verification, and some synthesis support for the
  • Flex-Logix in-house interconnect switch/bitcell modeling
  • eFPGA reconfigurable building block (RBB), block memory (BRAM), and IP netlist
  • InferX reconfigurable tensor processor block
  • InferX high-speed configurator
  • MBIST/Repair RTL generation for memory IPs

Required Experience  

  • BS/MSEE/CE/CS with a minimum of 3 years of experience in RTL design or functional verification
  • Experience with starting designs from scratch
  • Extensive experience coding Verilog, running simulation, and debugging simulation failure
  • Experience interfacing with internal and 3rd party IP suppliers
  • Experience running Lint, CDC, and other static quality checks
  • Working knowledge of System Verilog
  • Experience scripting in Python or Perl
  • Work effectively with verification team to deliver a high-quality RTL which is easy to maintain, scalable, and with high-speed performance
  • Must be passionate about doing this job: wanting to change the world and work hard doing it
  • Must be entrepreneurial in spirit and an innovative problem solver

Preferred Experience 

  • Knowledge of computer architecture, especially in systolic arrays
  • Familiarity with memory architecture in SoCs – Experience with DDR and PCIe standards
  • Experience with FPGA design and emulation
  • Experience with FPGA and ASIC EDA tools
  • Experience interfacing with back-end teams (silicon engineering)
  • Familiarity with C or C++ coding
  • Experience with DMA, DDR controllers, NoC configuration, and other 3rd party IP
  • Logic/physical synthesis of RTL
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To view the job application please visit

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