SoC Verification Manager/Director

Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.
The India Technology Center leads all SoC development at Achronix Semiconductor, working on end-to-end design development, from architecture development all the way to chip tape-out for Achronix’s Speedster and Speedcore class of FPGAs. The team owns the design of various high-speed SerDes, memory and NoC architecture subsystems, maximizing the data bandwidth and latency in and out of Achronix FPGAs.
Job Description/Responsibilities
The opening is for a verification Sr. Manager/Director who is responsible for overall SoC verification and performance modeling for Achronix’s Speedster class of FPGAs. This a high-visibility role with critical responsibilities and requires a high level of expertise and commitment, plus very good communication and presentation skills. This employee is expected to be self-driven, constantly looking to set the bar higher, and a driver of excellence!

Apart from people management responsibilities, the employee will drive methodology and own QA for the verification of all subsystems in the SoC, spanning memory subsystems like DDR5, GDDR6 and HBM2/2e, SerDes subsystems such as PCIe Gen3/4/5, CXL, 100G/400G/800G Ethernet and multi-standard PCS, and chip-level NoC connectivity. The primary responsibilities include:

Manage the SoC verification team, working with the individuals on their development and learning, and managing assignments to specific projects and subsystems
Drive methodologies and best practices across all SoC verification, including testbench architectures, test plan structures, migration from subsystem to full chip, etc.
Own and drive full-chip-level verification
Drive SoC system-level performance modeling
Own QA for verification of all subsystems and the full chip
Post-Si support
Mentor other engineers
The employee is also expected to participate regularly in interactions with global teams spanning systems, software, and product engineering

Required Skills
Expertise in leading verification of multiple complex interface such as PCIe, GDDR6, chip-level buses, etc., for high-performance chips in FPGA/ML/AI domain
Experience managing a large team and looking after their growth, as well allocating resources to projects
Expertise in performance modeling, with a strong background in system-level performance test creation and decision making on trade-offs
Excellent written and verbal communication skills
Intrinsically driven and always raising the bar
Ability to take high-level complex and/or long-term goals, break them down to smaller goals and tasks, and plan them out. Must be able to see the big picture.
Experience with post-Si bring-up and debug
Strong automation and scripting experience, especially in Python and/or Perl is a plus
Thrives in a dynamic and fast-paced environment, with a pro-active mindset
Education and Experience
Preferred BS/MS + 16+ years of experience in RTL design and verification
At least eight years of experience in managing teams and executing complex projects