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2023 Engineering Internship – CPU Verification

2023 Engineering Internship – CPU Verification
by Admin on 12-06-2022 at 6:05 pm

Do you want to help Arm and its partners to build outstanding products?

Arm’s Sophia Antipolis design centre is located in one of the most appealing parts of France, the French Riviera, at the heart of Europe’s largest and most dynamic technology park. Surrounded by mountains and the Mediterranean Sea, this outstanding design centre has delivered leading products from Arm’s Cortex (TM) CPU family. These CPUs power some of the world’s best-selling smartphones, tablets and gaming systems, using technology that has taken user experience and performance to another level.

We aim to help you increase your potential by taking part in the development of the next generation of CPUs that will appear in the most desirable products over the next 3 years and give you an incredible variety of potential career paths. CPU Sophia hardware design team is a good combination of very expert engineers and some of the most enthusiastic and hardworking graduates, coming from the best engineering schools. Collectively, the team is highly creative, collaborative, delivery-orientated and committed.

Job Overview

Whether improving existing or creating new hardware, you will always be provided with the most exciting and enriching topics that could end up in a real project. Our main focus is to conceive, build and test the most energy efficient hardware that meets our partner’s expectations in terms of Area, Frequency and Performance. 

A wide variety of internship topics is offered in microarchitecture and design for which you will have to show and grow strong development capabilities in CPU microarchitecture knowledge and C/C++ and HDL languages. 

We will support you with continuous learning and development and you will be encouraged to achieve your professional goals. 


  • To start, you will need to take ownership of one of the following topics:
  • [2023-D1] Efficient support of complex access patterns of Scalable Matrix Extension
  • [2023-D2] Efficiency Verification and Improvements of Performance Driven Power Management features at Core Block Level
  • [2023-D3] Hardware Stack protection mechanism
  • [2023-D4] Implement Register Bank prefetching techniques
  • [2023-D5] L2 Translation Lookaside Buffer Clustering improvements

You will be required to become familiar with the subject, think about possible implementations and design the most promising one. One of our brilliant engineers will mentor you during your journey and you will share your findings during regular presentations and a final report.

Required Skills and Experience

  • Students in their last year of Masters (BAC+5 or equivalent) and available for a 5 to 6-month internship.
  • Students in electronic engineering, computer engineering, computer science, or another relevant field, but other degrees may also be considered based on experience.
  • A passion for new technologies, high-end mobile computing, and innovation.
  • An understanding of computer architecture fundamentals.
  • Knowledge of Microprocessors/CPU microarchitecture
  • Knowledge of Microprocessor/ASIC systems
  • Familiarity with a hardware description language such as VHDL or Verilog/SystemVerilog.
  • Use of a Linux environment and at least one programming/scripting language.
  • Fluency in English

“Nice To Have” Skills and Experience

  • Basic Knowledge of Arm architecture. 
  • Assembly language programming, ideally in Arm assembler.
  • Knowledge of C programming.
  • Use of UNIX and shell programming.
  • Familiarity with a versioning environment such as git.
  • Ability to express ideas and communicate effectively.
  • Good interpersonal skills.


  • Salary – 1750 euros / month 
  • Lunch vouchers
  • 1 day off (authorized leave) / month
  • Transportation 50% reimbursement
  • Mobility subsidy if eligible
  • Work Council subsidy /meyclub

Internship duration

  • 5 to 6 months
Apply for job

To view the job application please visit

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