Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools

There is ample evidence that technologies such as high-performance computing, next-generation servers, and AI accelerators are fueling unprecedented demands in data processing speed with massive data storage, lower latency, and lower power. Heterogeneous system integration, more commonly called 2.5 and 3D IC design, promises to address these demands. As there is no “free lunch”, these new design approaches create similarly unprecedented demands associated with manufacturability and cost. It turns out the solution to this dilemma requires a combination of advanced design tools and purpose-built IP. One company stands apart with deep technology in both areas. Let’s explore how Synopsys brings multi-die integration closer with its 3DIO IP Solution and 3DIC tools.

Framing the Problem

There are two fundamental challenges to be met in order to bring heterogeneous system integration closer to reality – packaging and interconnect. Let’s examine the key requirements of each.

The need to process massive quantities of data is a driver for advanced packaging. There are many approaches here. 2.5D and 3D packaging have gained popularity as prominent solutions. In the 2.5D approach, two or more chips are side by side with an interposer connecting them. The interposer acts as a high-speed communication interface, creating greater flexibility to combine functions in one package.

For 3D IC, chips are connected with vertical stacking. This improves performance and functionality, allowing the integration of chiplets with multiple layers. A key trend is to shrink the bump pitch between the chiplets.  This improves interconnect distances and related parasitics.

All of these new design requirements and advanced packaging approaches have given rise to a significant change in interconnect strategies from traditional copper uBUMP to the most advanced uBUMP using 40um pitch, scaling even further down to 10um.

For 2.5D design, the connection between chips is made through redistribution layers on the interposer.  The distance between chips is usually around 100um. For 3D, the use of vertical stacking allows for direct connection between two chips, reducing the distance to less than 40um. The result is a much smaller substrate.

With this approach, IO no longer needs to be placed at the edge of the chip. Also, by using hybrid bond technology the vertical connection between chips is even tighter. Hybrid bonding connects dies in packages using tiny copper-to-copper connections (<10um).  

Synopsys has released an informative technical bulletin on all these trends. A link is coming. The figure below is taken from that document and shows these significant scaling trends.

Addressing the Problem

Taming these design challenges requires a combination of advanced EDA tools and specialty IP. Together, these two approaches form a winning design approach. Synopsys is well-known for its 2.5/3D design tools. Its 3D IC Compiler is a key enabler for multi-die integration. It turns out the design methodology required spans many disciplines. More on that in a moment. First, let’s examine how Synopsys brings multi-die integration closer with its 3DIO IP Solution.

This IP is specially tuned for multi-die heterogeneous integration, enabling the optimal balance of power, performance and area to address the packaging demands of 3D stacking. It turns out the 3DIO IP enables faster timing closure as well.

To better understand how it works, here are the key components of the solution:

• Synopsys 3DIO includes a synthesis friendly Tx/Rx cell compatible with Synopsys standard cell libraries and a configurable charge device model for optimal ESD protection. As the number of IO channels increases, the optimized Synopsys 3DIO solution leverages the automatic place and route environment to place and route the IOs directly on the BUMP. The solution supports both 2.5D and 3D packaging using uBUMP and hybrid BUMP. The Synopsys 3DIO cell supports a high data rate and offers the lowest power solution, with an optimal area that fits within the hybrid BUMP area.
• Synopsys Source Synchronous 3DIO (SS3DIO) extends the synthesizable 3DIO cell solution with a clock forwarding functionality to aid in lower bit error rate and ease timing closure between dies. The SS3DIO offers scalability to create custom-sized macros with optimal PPA and ESD. The TX, RX, and clock circuits support matched data and clock path, with data launched at the transmitting clock edge and captured at the corresponding receiving clock edge.
• Synopsys Source Synchronous 3DIO PHY is a 64-bit hardened PHY module with inbuilt redundancy, optimized for the highest performance. The 3DIO PHY with CLK forwarding reduces bit error rate and eases implementation along with optimal placement of POWER/CLK/GND BUMP.

The figure below, also taken from the Synopsys technical bulletin provides an overview of how the Synopsys 3DIO IP Solution helps a with a variety of design challenges.

With new packaging technologies and increased density of interconnects, there is a significant rise in the IO channels for a given die area. The corresponding decrease in IO channel length increases performance but gives rise to the need for a more streamlined interface. The Synopsys 3DIO IP Solution provides a way to implement tunable, integrated multi-die design structures.

To Learn More

Addressing the challenges of heterogeneous system integration requires a combination of advanced design tools and IP that is optimized for this new design style. Synopsys provides strong offerings in both areas. As mentioned, a cornerstone of tools is the Synopsys 3DIC Compiler. You can learn more about Synopsys 3DIC Compiler here.  In the area of overall design flow, there is an excellent webinar that Synopsys recently presented with Ansys that delves into all the aspects of multi-die design. You can catch the replay of that webinar here.

You can access the technical bulletin that provides more detail on Synopsys 3DIO Solution here. And you can explore more about this IP, including access to the Synopsys 3DIO IP Solution datasheet on the Synopsys website here.  And that’s how Synopsys brings multi-die integration closer with its 3DIO IP Solution and 3DIC tools.