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I'm trying to know how recent technologies for example tsmc 40nm LP dope it's substrate. does it use epitaxial layer plus heavily doped substrate? or using lightly doped one?
Glad to help out. I'm sure that companies like TSMC will still keep their IC fabrication process and steps secret enough to keep their competitors in the dark.
This is usually a cost and mechanical strength decision as CMOS substrates should not have any significant DC current flowing in it.
Light and Heavy doped are relative terms.
One extreme would bipolar wafers with < 10 ohm substrates on 111 wafers.
The other extreme would be SOI wafers with >100 ohm substrates.
Substrate doping in standard CMOS is in the 10-50-100ohm range. (that is per cubic volume).
This usually results in a DC resistance between the substrate contact and the device substrate in the 1-100ohm range
when placing generous -thru- DRC minimum substrate taps.
A much lower resistance Si wafer is more expensive and fragile and is not required for CMOS.
(unlike a bipolar or some bicmos technology that can have significant substrate currents in normal device operation.)
A much higher resistance is also not needed as it is much more expensive.
Once you go to high Rho substrates, you need to consider substrate biasing at each devices more closely,
and this may require extra substrate connections ( think SOI ). This is technically faster, but at a significant cost.
