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why not do FEOL at one foundry with faster (or say best in some concerned parameter) devices and transfer wafer to other foundry with better BEOL (small metal pitching and low defects) and if required 3rd part of MEMS, RRAM, MRAM, etc. can be done in other foundries which are specialized in it
Split manufacturing already proposed to ensure security by not allowing any of that foundry to have full layout of IC
I am more interested if power/area/speed/cost can be improved by getting best/cheapest of FEOL & BEOL from different foundries (just like designers put together different hard IPs to make SoC)
There are examples of Samsung licensing finfet process to GF, but GF may still have to work on ramping it up .. what if Samsung works on ramping up FEOL & GF works on ramping up BEOL
why not do FEOL at one foundry with faster (or say best in some concerned parameter) devices and transfer wafer to other foundry with better BEOL (small metal pitching and low defects) and if required 3rd part of MEMS, RRAM, MRAM, etc. can be done in other foundries which are specialized in it
Split manufacturing already proposed to ensure security by not allowing any of that foundry to have full layout of IC
Management issue can be handled later if output is worth ... blame game can even happen in design case where say simple I/O IP from another third vendor can make full SoC useless
Also no need to use two big foundries .. Big foundries can be main controller & validate the flow of other small foundries doing part of flow
Technically can you gain performance? Any issue with contamination during transport? Will it be cost-effective and faster to ramp-up yield independently?
Yield problem might not necessarily be management issue. It could be realistic problem on die. You need a specific PDK for such dual foundry solution. Any variation in one side could contribute to yield loss. However normally both sides will drift a bit from time to time. And then it is hard to learn which is key source of the problem. The cross correlation is simply blocked by security concerns. Machine history is not available to another foundry for sure.
Technically you can gain performance by a big value added solution. E.g. a RRAM array on top of back-end.
Issue with contamination: Yes. You need to seal your wafer with sacrificial layer before transportation. Not a big deal in my opinion.
SOC yield depends on both side. You need a process which gives the exact performance you show to the designers with your models. Without back-end or front-end, even if you get defect free, you still don't know where your device performance lands.
RRAM is an exception. It can be on top of metal 3.
MEMS is normally huge. So it can not be integrated into a single die.
Their flow starts with formation of III-V material on 8" Si wafers, then it goes to GF fab in Singapore for CMOS processing, then comes back to form III-V transistors. So, yes, it needs a special PDK for combined process flow, dealing with the contamination, etc. But can be done if there is strong value added proposition.
Split Manufacturing (aka "split fab") is a very promising idea! High-volume manufacturers don't want to experiment with novel materials and/or processes, but small experimental fabs often can't produce latest-node features. Split Fab offers best of both. Let the big fab build the base wafer, then ship to the small fab for their "special sauce." Some difficulties have already been mentioned: contamination, etc. Another hurdle is that fabs don't like to reveal their proprietary "recipes" to other fabs that might compete. However, I can verify that some important customers are working hard to make Split Fab a reality.
Another hurdle is that fabs don't like to reveal their proprietary "recipes" to other fabs that might compete. However, I can verify that some important customers are working hard to make Split Fab a reality.
In this model why fabs have to reveal their proprietary "recipes" to other fabs. First fab has to to give to second fab just the wafer manufactured till stage (say after FEOL) without disclosing how they got it. Same for vice versa ... only thing to be disclosed will be specs that second fab shouldn't have temperature/stress or any other parameter which will affect the FEOL of first fab
I don't want you reveal the name, can atleast tell motivation of "important customers" = "govt agencies trying for security of some critical ICs (as in IARPA's TIC )" or "design houses trying for performance gain" or "fabs themselves trying to outsourcing part of manufacturing line for concentrating capacity on critical steps"
Certainly IARPA's TIC program is a huge player, for security. Other customers want:
1) Specialized structures not otherwise available such as high-value capacitors, precision resistors, inductors
2) Unusual materials such as magnetics, organics, graphene, nano-tubes
3) TSV insertion, 2.5 and 3D assembly
It's worth noting that "split fab" is already being used in many cases. Alignment, planarity, and "blame game" do not seem to be problems.
