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Samsung HBM4 4nm Logic Die Test Yield Exceeds 40%

Fred Chen

Moderator
While the foundry (semiconductor contract manufacturing) process is applied to the 'logic die', which serves as the brain of the 6th generation high-bandwidth memory (HBM4), for the first time, it is known that the test yield of the logic die produced by Samsung Electronics' foundry division is stable. Analysts say that Samsung Electronics' HBM4 12-layer development and mass production, which has lagged behind in the HBM technology competition, will gain momentum.

According to industry sources on the 16th, the test production yield of logic dies produced by Samsung Electronics' foundry 4nm (nanometer, 1 billionth of a meter) process has exceeded 40%. Considering that the initial test production yield of Baidu chips, which are being mass-produced with the 4nm process, was in the mid-to-late 10% range, this is encouraging. Jeon Young-hyun, head of Samsung Electronics' DS (semiconductor) division (vice chairman), is known to have delivered a message of encouragement regarding the recent performance of the foundry division.

The foundry division has introduced a large number of new processes that can improve performance while producing this logic die. An official from the semiconductor industry explained, "The initial test production yield of 40% is a good number that is enough to push ahead with the business right away," adding, "Usually, (the foundry process) starts at the 10% level and the yield increases as it goes through mass production."

Samsung Electronics, which has surrendered its leadership to SK hynix and Micron in the HBM3E (5th generation HBM) market, is focusing on HBM4 logic die production. HBM4 logic dies are equipped with foundry micro-processing to improve chip performance and can be produced according to the design desired by customers, allowing them to flexibly respond to the 'customized HBM' market, which is rapidly increasing in demand from global Big Tech companies. SK hynix and Micron have to rely on TSMC, a foundry company, but Samsung Electronics can demonstrate its strengths by having its own foundry technology.

Now, the success or failure of Samsung Electronics' HBM4 business depends on the 10nm-class 6th generation (1c) DRAM developed by the Memory Division. The HBM4 12-speed product is equipped with 1c DRAM along with a logic die. Samsung Electronics' competitor SK hynix is using the previous generation DRAM, 1b DRAM, for HBM4, and if Samsung Electronics can mass-produce 1c DRAM stably, it can gain an advantage in HBM4 performance.

Packaging that combines 1c DRAM and logic die to produce them in the form of a final product is also key. Samsung Electronics uses a different packaging method than SK hynix. Samsung Electronics uses 'Advanced Heat-Pressed Non-Conductive Adhesive Film (TC-NCF)' technology, which is a method of laying film-type materials on top of each chip up to a 12-layer HBM product. However, this packaging method is evaluated as having difficulty controlling heat generation.

A semiconductor industry official said, "Samsung Electronics still has the task of stabilizing the DRAM installed in HBM and the technology that packages it."

Meanwhile, SK hynix took the throne of the DRAM market for the first time since its foundation in the first quarter with an HBM market share of more than 70%. According to Counterpoint Research, a market research firm, SK hynix accounted for 36% of the DRAM market share in the first quarter of this year, followed by Samsung Electronics with 34%. SK hynix has produced HBM4 12-layer products and sent samples to customers.

 
Does yield improvements usually come from a design change or a process change?

The article says that "Yield usually starts at 10% and goes up through mass production"

How come the process isnt "perfected" before going into mass production?

That seems unfathomable to me , we would close down if go below 98% yield in any area of production.
 
Does yield improvements usually come from a design change or a process change?

The article says that "Yield usually starts at 10% and goes up through mass production"

How come the process isnt "perfected" before going into mass production?

That seems unfathomable to me , we would close down if go below 98% yield in any area of production.
Probably in the race at leading edge (or actually any popular advanced node) to be "first" (or simply participate), yield requirements were loosened. Not even months' delay from new design tapeout.
 
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There was an interesting statement possibly alluding to relative die size:

According to industry sources on the 16th, the test production yield of logic dies produced by Samsung Electronics' foundry 4nm (nanometer, 1 billionth of a meter) process has exceeded 40%. Considering that the initial test production yield of Baidu chips, which are being mass-produced with the 4nm process, was in the mid-to-late 10% range, this is encouraging.
 
There needs to be an entire course taught at management and business schools on Samsung semi . I don’t understand how they lost competitiveness in all aspects of their business in such a short period of time.
 
There needs to be an entire course taught at management and business schools on Samsung semi . I don’t understand how they lost competitiveness in all aspects of their business in such a short period of time.
Intel as well how can you go from +2 nodes ahead to 2 nodes behind and loosing the world dominating position.
 
Intel as well how can you go from +2 nodes ahead to 2 nodes behind and loosing the world dominating position.
In all seriousness - when was Intel a full 2 nodes ahead?

In "recent times", they had the first "real" 14nm process. But TSMC, GloFo, and Samsung were not >1 node behind.

Around the 32nm era, they were maybe 1 year ahead of TSMC's 28nm class process (though Intel's process was probably higher performance).

From 180nm through 65nm Intel IIRC was never more than 1 year (half node) ahead of AMD. .35 micron/.25 micron they might have achieved one node ahead briefly.
 
Strange article. so many urban legends about Samsung, its hard to track.

On memory technology, I believed techinsights shows all three companies have similar bit density/cell size. Samsung is not behind
On HBM3, the logic die is typically 16nm or older I believe. I dont think you need N4 for logic die for HBM4 (correct me if I am wrong).

N4 is Samsungs last Finfet technology, correct? what are some products made on that?

Yields are not always 100% correlated to die size for a variety or reasons .... but reported yields are almost universally wrong. Right now I would guess Intel has a 18A product at 50% yield and another at zero yield. and that is not even including the "modified" test programs to get yields acceptable to management "if we ignore the cache, high power, and we work around timing issues and run it at 500Mhz, the yields are 60%"

Unless you see the internal document on yield issues and units/wafer start .... which some people have access to ... ... take the yield number with a grain of salt. Just an opinion
 
In all seriousness - when was Intel a full 2 nodes ahead?

In "recent times", they had the first "real" 14nm process. But TSMC, GloFo, and Samsung were not >1 node behind.

Around the 32nm era, they were maybe 1 year ahead of TSMC's 28nm class process (though Intel's process was probably higher performance).

From 180nm through 65nm Intel IIRC was never more than 1 year (half node) ahead of AMD. .35 micron/.25 micron they might have achieved one node ahead briefly.
Looks like I remember something off my mind after searching online Intel had a 2 year lead vs rest of the industry.
 
Strange article. so many urban legends about Samsung, its hard to track.

On memory technology, I believed techinsights shows all three companies have similar bit density/cell size. Samsung is not behind
On HBM3, the logic die is typically 16nm or older I believe. I dont think you need N4 for logic die for HBM4 (correct me if I am wrong).

N4 is Samsungs last Finfet technology, correct? what are some products made on that?

Yields are not always 100% correlated to die size for a variety or reasons .... but reported yields are almost universally wrong. Right now I would guess Intel has a 18A product at 50% yield and another at zero yield. and that is not even including the "modified" test programs to get yields acceptable to management "if we ignore the cache, high power, and we work around timing issues and run it at 500Mhz, the yields are 60%"

Unless you see the internal document on yield issues and units/wafer start .... which some people have access to ... ... take the yield number with a grain of salt. Just an opinion
Well, their newest DRAM node 1c is reportedly delayed a second time, until October at the earliest, due to capacitor leakage which in turn will delay HBM4 that SK Hynix is already sampling. Micron and SK Hynix are already in mass production of their comparable 1c (1-gamma) node. Samsung has zero percent of the HBM3e sales to Nvidia due to quality issues. Management has been turned over twice in a year. It’s currently not smooth sailing there and this capacitor issue, if true, seems like a huge problem to rectify. Samsung’s flagship phones are using Micron DRAM. That’s wild
 
Strange article. so many urban legends about Samsung, its hard to track.

On memory technology, I believed techinsights shows all three companies have similar bit density/cell size. Samsung is not behind
On HBM3, the logic die is typically 16nm or older I believe. I dont think you need N4 for logic die for HBM4 (correct me if I am wrong).


tsmc can provide both 12FFC+ and N5 solutions for HBM4 depends on customers' need.
 
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