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Process engineering from 1990s: what do these steps mean?

J

jms_embedded

Well-known member
I'm trying to decode what the various steps are from one of the MIMAC datasets, published in 1995 (see associated report)

The process names and tool groups (in parentheses) from one of the microprocessor products (set4.xls, Product 1) are listed below. I can guess at some of them (Nitr = nitride, Dep = deposition, Dehyd = dehydration bake, Impl = ion implant, Align = exposure with a mask aligner, Coat = photoresist coat) but what are some of the others: Phosw, Dip, D_B, Pre_CD, Deglz, APS, Silox, Sinter, etc. and what some of the tool group names might mean (QLESS or DFA2 for example; I can guess PE = photoexposure, WET = wet bench, DRY = dry etch, etc.)

Any clues would be helpful; I'm not a process engineer but I'm guessing some of you are or have experience in this field.

A01_FSI_Clean (FSI_)
A02_26_Init_Oxid (DFA2_)
A03_FSI_Clean (FSI_)
A04_26_Phosw_Coat (C1-9_)
A05_26_Phosw_Align (PE1-5_)
A06_26_Phosw_D_B (D1-9_)
A07_26_Phosw_Pre_Ins (QLESS_)
A08_26_Phosw_Impl (ION1-3_)
A09_26_Phosw_Bk_etch (WET3_)
A10_Piranha_Strp (QLESS_)
A11_FSI_Clean (FSI_)
A12_26_Phosw_Diff (DFB1-2_)
A13_FSI_Clean (FSI_)
A14_Nitr_Dep (DFE1-2_)
A15_Nitr_Dehyd (LPS1_)
A16_Nitr_Coat (C1-9_)
A17_Nitr_Align (PE1-5_)
A18_Nitr_D_B (D1-9_)
A19_Nitr_Pre_CD (QLESS_)
A20_Nitr_Etch (DRY1-2_)
A21_Piranha_Strp (QLESS_)
A22_26_P+_Fld_Coat (C1-9_)
A23_26_P+_Fld_Align (PE1-5_)
A24_26_P+_Fld_D_B (D1-9_)
A25_26_P+_Fld_Pre (QLESS_)
A26_26_P+_Fld_Impl (ION1-3_)
A27_Piranha_Strp (QLESS_)
A28_FSI_Clean (FSI_)
A29_26_Local_Oxid (DFB3_)
A30_26_Nitr_Strp (DRY1-2_)
A31_26_Nitr_Dip (WET3_)
A32_FSI_Clean (FSI_)
A33_Gate_Oxid (DFA4_)
A34_CD_Impl (ION1-3_)
A35_Poly_Dep (DFE3-4_)
A36_Poly_Dope (DFC2-3_)
A37_HF_Deglz (FSI_)
A38_Poly_Dehyd (LPS1_)
A39_Poly_Coat (C1-9_)
A40_Poly_Align (PE1-5_)
A41_Poly_D_B (D1-9_)
A42_Poly_Pre_CD (QLESS_)
A43_Poly_Etch (TEG2_)
A44_Piranha_Strp (QLESS_)
A45_Poly_Post_CD (OSICD2_)
A46_FSI_Clean (FSI_)
A47_Poly_Oxid (DFB4_)
A48_P+_Coat (C1-9_)
A49_P+_Align (PE1-5_)
A50_P+_D_B (D1-9_)
A51_P+_Pre (QLESS_)
A52_26_P+_Impl (ION1-3_)
A53_Piranha_Strp (QLESS_)
A54_26_N+_Coat (C1-9_)
A55_26_N+_Align (PE1-5_)
A56_26_N+_Dev_Bake (D1-9_)
A57_26_N+_Pre (QLESS_)
A58_26_N+_Impl (ION1-3_)
A59_26_N+_PR_Ash (DFA1_)
A60_Piranha_Strp (QLESS_)
A61_26_Field_Silox (ASM2_)
A62_Silox_Scrub (SCRUB_)
A63_Reflow (DFC1_)
A64_APS_Deh (LPS1_)
A65_APS_Coat (C1-9_)
A66_APS_Align (PE1-5_)
A67_APS_Dev_Bake (D1-9_)
A68_APS_Pre (QLESS_)
A69_APS_Bake (BLU1_)
A70_APS_Etch (AME135_)
A71_Piranha_Strp (QLESS_)
A72_Alum_Clean (WET5_)
A73_26_Alum_Dep (WET5_)
A74_26_Alum_Coat (C1-9_)
A75_26_Alum_Align (PE1-5_)
A76_26_Alum_Dev_Bake (D1-9_)
A77_26_Alum_Pre_CD (QLESS_)
A78_26_Alum_Bake (BLU1_)
A79_26_Alum_Etch (AME46_)
A80_26_Dry_Strip (MEG1-2_)
A81_Solvent_Strip (WET1_)
A82_26_Alum_Post_CD (OSICD2_)
A83_Sinter (DFC4_)
A84_26_Silox_Dep (ANC1_)
A85_26_450_Anneal (DFC4_)
A86_26_Silox_Coat (C1-9_)
A87_26_Silox_Align (PE1-5_)
A88_26_Silox_Dev_Bake (D1-9_)
A89_26_Silox_Pre (QLESS_)
A90_26_Silox_Bake (BLU1_)
A91_26_Silox_Etch (WET3_)
A92_Solvent_Strip (WET1_)
 
Based on Pre_CD being after various litho related ops and before etch, my best guess is that it is just an inspection step. Silox might be wet SiO2 growth. I don't know if self aligned source/drains were a thing in the 90s, but if this is before that, then Phosw might be N-well formation. Although I suspect the P+ and N+ steps that happen after the poly loop might be more likely to be the well and S/D formation steps.
 
nghanayem said:
I don't know if self aligned source/drains were a thing in the 90s, but if this is before that, then Phosw might be N-well formation.
Click to expand...
All the microprocessors used poly self-aligned gate... well, at least Intel did for the 4004, and MOS Technology did for the 6502, and that was back in the 1970s.

CD = "critical dimension" measurement?
 
Phosw = Phosphorus Well (n-well)
Nitr_Dip = Hot Phosphoric Etch
D_B = Develop & Hard Bake
Pre_CD = Pre-etch (or processing) Critical Dimension (of PR, Nitr, etc.)
Deglz = Deglaze of Phosphorus doping excess on top of Polysilicon (for PR adhesion & consistent polysilicon sheet resistance)
APS = Aluminum (or Al Alloy) to Poly & Silicon (contact mask)
Silox = Silicon Oxide (doped or undoped)
Sinter = Alloy AlSi metal to polysilicon & silicon contacts (400*F+)
PE = Perkin Elmer Projection Aligner #1-#5
DFA2 = Diffusion Furnace #A2
TEG2 = Tegal Etcher #2
BLU1 = Blue M Oven #1
C1-9 = Coater Tracks #1-#9
FSI = Fluoroware Semiconductor International (cleans/dries)
DRY1-2 = Drytech Etcher #1-#2
Most of the parentheses are specific equipment manufacturers or process function...
 
jpb_44 said:
Phosw = Phosphorus Well (n-well)
Nitr_Dip = Hot Phosphoric Etch
D_B = Develop & Hard Bake
Pre_CD = Pre-etch (or processing) Critical Dimension (of PR, Nitr, etc.)
Deglz = Deglaze of Phosphorus doping excess on top of Polysilicon (for PR adhesion & consistent polysilicon sheet resistance)
APS = Aluminum (or Al Alloy) to Poly & Silicon (contact mask)
Silox = Silicon Oxide (doped or undoped)
Sinter = Alloy AlSi metal to polysilicon & silicon contacts (400*F+)
PE = Perkin Elmer Projection Aligner #1-#5
DFA2 = Diffusion Furnace #A2
TEG2 = Tegal Etcher #2
BLU1 = Blue M Oven #1
C1-9 = Coater Tracks #1-#9
FSI = Fluoroware Semiconductor International (cleans/dries)
DRY1-2 = Drytech Etcher #1-#2
Most of the parentheses are specific equipment manufacturers or process function...
Click to expand...
Oh wow, I'm glad I asked -- this is great! I figured out a couple of them (e.g. DF was probably Diffusion Furnace, and D_B was probably develop/bake) but was stuck on APS.
 
jpb_44 said:
Phosw = Phosphorus Well (n-well)
Nitr_Dip = Hot Phosphoric Etch
D_B = Develop & Hard Bake
Pre_CD = Pre-etch (or processing) Critical Dimension (of PR, Nitr, etc.)
Deglz = Deglaze of Phosphorus doping excess on top of Polysilicon (for PR adhesion & consistent polysilicon sheet resistance)
APS = Aluminum (or Al Alloy) to Poly & Silicon (contact mask)
Silox = Silicon Oxide (doped or undoped)
Sinter = Alloy AlSi metal to polysilicon & silicon contacts (400*F+)
PE = Perkin Elmer Projection Aligner #1-#5
DFA2 = Diffusion Furnace #A2
TEG2 = Tegal Etcher #2
BLU1 = Blue M Oven #1
C1-9 = Coater Tracks #1-#9
FSI = Fluoroware Semiconductor International (cleans/dries)
DRY1-2 = Drytech Etcher #1-#2
Most of the parentheses are specific equipment manufacturers or process function...
Click to expand...
very good. I think I worked on most of these processes LOL
 
Am I correct in concluding that this is a 9-mask-layer CMOS process with 1 metallization layer? (9 times through coat/align/dev/bake/pre_cd inspection)

- Phosw = N-well
- Nitr = Nitride
- P+ field (what's the difference between this step and the later P+ step? Both involve ion implantation.)
- Poly = polysilicon
- P+
- N+
- APS = contact layer
- Alum = aluminum (metal layer)
- Silox = silicon dioxide passivation

Looks somewhat similar to the depletion-load NMOS process used in the 6502. (7 layers: diffusion, depletion, buried-contact, polysilicon, pre-ohmic contact, metal, passivation)
 
Last edited:
  • Any clues about how old this process might be? My conclusion is CMOS 9 mask layers including 1 metal layer probably means mid-late 1980s, still operating in early 1990s. Given my limited knowledge, this doesn't seem like a cutting-edge microprocessor, so not Intel/AMD but maybe a Motorola microcontroller or something similar from Zilog or National Semiconductor.

  • What's the difference between "P+_Fld" mask layer and "P+"? (process steps go phosphorus N-well, nitride, P+ Fld, polysilicon, P+, N+, APS=contact, aluminum, and Silox=passivation)

  • What's going on in steps 29-34? (presumably the abbreviations stand for local oxide, nitride strip, nitride dip, clean, gate oxide, and CD ion implant... I thought CD = critical dimension was an inspection step, but it's listed as part of the ion implant toolgroup)

  • A27_Piranha_Strp (QLESS_)
    A28_FSI_Clean (FSI_)
    A29_26_Local_Oxid (DFB3_)
    A30_26_Nitr_Strp (DRY1-2_)
    A31_26_Nitr_Dip (WET3_)
    A32_FSI_Clean (FSI_)
    A33_Gate_Oxid (DFA4_)
    A34_CD_Impl (ION1-3_)
    A35_Poly_Dep (DFE3-4_)
    A36_Poly_Dope (DFC2-3_)
What is the "dry strip" / "solvent strip" (steps 80 and 81 after aluminum layer lithography) and why is it used instead of Piranha solution like the earlier passes through lithography?
  • Is there a reason polysilicon and aluminum get an extra "Post_CD" inspection step? (steps 45 and 82)
 
Piranha solution attacks aluminum. Using it would destroy the pattern and contaminate the bath. The solvent used doesn't attack aluminum.

The post_CD is because those dimensions are so critical they need to be checked after etch.
 
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