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I want to explore complete physical design flow.
Please explain it in the below format
1 What are the input files required to each stage?
What are the output files generated from each stage?
What is the content in each file and the necessity of it.
Logical design is done first starting with a high-level language like C, C++, SystemC or RTL language
Logic synthesis is run taking the HLS or RTL code as input, technology file for input, standard cell library as input, and gate-level netlist as output
The digital portion of the netlist can be placed and routed with a P&R tool from Cadence/Mentor/Synopsys, taking as input: gate-level netlist, technology files, DFM rules. Output is a GDS II, OASIS, LEF, DEF and OpenAccess (Cadence) file. Prior to P&R you can do some manual or automatic floorplanning by arranging blocks like pieces of a jigsaw puzzle to minimize area and interconnect delays.
The interconnect and cell information is extracted to create a netlist for SPICE circuit simulation, and for Static Timing Analysis (STA) like PrimeTime (Synopsys)
The physical IC layout has to be validated for manufacturability with a Design Rule Checking tool like Calibre (Mentor Graphics), with inputs of the extracted netlist, rule decks form the foundry. Output is a report of violations and warnings.
Timing, power and area requirements must be closed, so there is often an iteration of these steps to reach closure
Power analysis is also run on the extracted design to provide feedback about dynamic power, static power and leakage power across various process corners.
Signal integrity issues like electro-migration and IR voltage drop are analyzed using the extracted design
With technology nodes at 20nm and smaller there are critical layout layers that must use Double Patterning Technology, so that comes into play during P&R and DRC
Thanks for the info.
Now I want to know info about each stage in detail.
Lets begin with synthesis first.
What is content in timing constraints and how they are written?
How the timing values or delays are considered in synthesis?
Is The delay or timing written are including net delay or gate delay or both?
In this stage there is no any routing done then on what basis we optimize the paths?
Also in this stage there is no any placement of blocks done but still there are delays written in constrain file and timing reports also generated. Please explain how this is done.
There's a good article over on Wikipedia on the physical design process with a few more details. It's a deep topic, and there are experts that use each of the EDA tools daily to reach design closure.
